Games Task Scheduler (GTS)
A multi-processor scheduling framework for games engines
ParallelContainers

Classes

struct  gts::FreeListNode
 An intrusive singly-linked list node used for free-lists. More...
 
struct  gts::MemoryStore
 The header for each Slab. More...
 
class  gts::BinnedAllocator
 A collection of BlockAllocators binned to size classes. More...
 
class  gts::ReadGuard< T, TAccessorSharedMutex, TGrowSharedMutex >
 A read-only item guarded by a mutex. The mutex is released on destruction. More...
 
class  gts::WriteGuard< T, TAccessorSharedMutex, TGrowSharedMutex >
 A read-write item guarded by a mutex. The mutex is released on destruction. More...
 
struct  gts::KeyValue< TKey, TValue >
 A key-value keyVal. More...
 
class  gts::ParallelHashTable< TKey, TValue, THasher, TAccessorSharedMutex, TGrowSharedMutex, TAllocator >
 A parallel hash table. Properties: More...
 
class  gts::ParallelVector< T, TSharedMutex, TAllocator >
 A obstruction-free parallel vector. Properties: More...
 
class  gts::QueueMPMC< T, TMutex, TAllocator >
 A multi-producer, multi-consumer queue. Properties: More...
 
class  gts::QueueMPSC< T, TMutex, TAllocator >
 A multi-producer, multi-consumer queue. Properties: More...
 
class  gts::QueueSPMC< T, TMutex, TAllocator >
 A multi-producer, multi-consumer queue. Properties: More...
 
class  gts::QueueSPSC< T, TAllocator >
 A single-producer, single-consumer queue. Properties: More...
 

Enumerations

enum class  gts::MemoryState : uint8_t { STATE_FREE = 0 , STATE_COMMITTED , STATE_IN_USE , STATE_ACTIVE }
 The states of memory object.
 

Functions

struct gts::GTS_ALIGN (GTS_MALLOC_ALIGNEMNT) PageHeader
 

Variables

constexpr uint32_t gts::GTS_MALLOC_ALIGNEMNT = 16
 

Detailed Description

Variable Documentation

◆ GTS_MALLOC_ALIGNEMNT

constexpr uint32_t gts::GTS_MALLOC_ALIGNEMNT = 16
constexpr

The alignment of all allocations.

Remarks
To aid the compiler's use of SIMD registers use (may also require a flag, see compiler documentation):
  • 16 for 128-bit registers (SSE)
  • 32 for 256-bit registers (AVX/2)
  • 64 for 512-bit registers (AVX512)